A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having a nitride film on a semiconductor substrate as an etching stopper film and to its manufacture method.
B) Description of the Related Art
A mobility of charge carriers in semiconductor is influenced by stress. For example, a mobility of electrons in silicon increases as a tensile stress increases, whereas it decreases as the tensile stress decreases. Conversely, a mobility of holes in silicon increases as a compressive stress increases, whereas it decreases as the compressive stress decreases.
Manufacture processes for a semiconductor device include generally a contact hole forming process of forming a contact hole through an interlayer insulating film covering a MOS transistor and exposing a MOS transistor electrode area. In order to form a contact hole with good controllability, the interlayer insulating film is made of an etching stopper film and an insulating film formed thereon. A nitride film having a tensile stress is mainly used as the etching stopper film.
As integrated circuit devices are highly integrated, electronic elements as constituent elements such as metal oxide semiconductor (MOS) transistors are made fine. As the miniaturization degree becomes high, a residual stress in an etching stopper film and the like causes a distinctive influence upon the characteristics of an electronic element such as a MOS transistor. It has been reported that a current drive performance of a MOS transistor can be improved by thickening a nitride film having a tensile stress and used as an etching stopper film (T. Ghani et al., A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors, 2003 IEDM Technical Digest, pp. 978-980).
As a nitride film used as an etching stopper film is thickened, it becomes difficult to control an etching process of forming a contact hole. In order to improve the characteristics of an n-channel MOS transistor without thickening a nitride film used as an etching stopper film, another means is desired to increase a stress to be applied to the channel region.
A general MOS transistor has side wall spacers on the side walls of an insulated gate electrode. An etching stopper film is deposited after the side wall spacers are formed. Namely, the side wall spacer exists between the etching stopper film and channel region. As the width of the side wall spacer is narrowed, it is expected that the etching stopper is positioned nearer to the channel region.
An increase in a tensile stress lowers the mobility of holes. In a CMOSFET integrated circuit, n- and p-channel MOSFETs are formed. As the tensile stress exerted by the etching stopper film on the channel region is increased, although the characteristics of the n-channel MOSFET are improved, the characteristics of the p-channel MOSFET are degraded.
Japanese Patent Laid-open Publication No. 2003-86708 has proposed to use a stress controlled film wherein an n-channel MOSFET is covered with a film having a tensile stress and a p-channel MOSFET is covered with a film having a compressive stress.
FIG. 5 is a schematic diagram showing the CMOS structure proposed in Japanese Patent Laid-open Publication No. 2003-86708. For example, an active region isolation trench is formed in a surface layer of a p-type silicon substrate 111, and an insulating film such as an oxide film is filled in the trench to form a shallow trench isolation (STI) region 112. Desired ions are implanted in active regions defined by the STI region 112 to form a p-type well 113 for an n-channel MOSFET and an n-type well 114 for a p-channel MOSFET. The surface of the active region is thermally oxidized to form a gate insulating film 115. After the gate insulating film is formed, a polysilicon layer is deposited to form a gate electrode layer. By using a resist pattern, the gate electrode layer and gate insulating film are patterned to form a gate electrode Gn and underlying gate insulating film 115 of the n-channel MOSFET and a gate electrode Gp and underlying gate insulating film 115 of the p-channel MOSFET. Desired ions are implanted into n- and p-channel MOSFET regions to form an n-type extension region 121n in the n-channel MOSFET region and a p-type extension region 121p in the p-channel MOSFET region.
Thereafter, an insulating film such as a silicon oxide film is deposited and anisotropic etching is performed to form side wall spacers SW on the side walls of the gate electrode. After the side wall spacers are formed, impurities of desired conductivity types are again implanted in the n- and p-channel MOSFET regions to form n-type source/drain diffusion layers 122n in the n-channel MOSFET region and p-type source/drain diffusion layers 122p in the p-channel MOSFET region.
Thereafter, a metal layer capable of silicidation such as cobalt is deposited to conduct a silicidation reaction, an unreacted metal layer is removed, and then the silicidation reaction is again conducted and completed to leave a silicide layer SL on the gate electrode G and source/drain regions 122. The n-channel MOSFET region is covered with an etching stopper layer 125n which is a nitride film having a tensile stress, and the p-channel MOSFET region is covered with an etching stopper layer 125p which is a nitride film having a compressive stress.
This structure can exert a tensile stress on the n-channel MOSFET region and a compressive stress on the p-channel MOSFET region. These stresses improve the characteristics of MOSFETs.
Japanese Patent Laid-open Publication No. 2004-127957 discloses the structure that the side wall spacer is made of a lamination of first and second insulating films, a retracted portion is formed on the first insulating film through selective etching, and after silicide regions are formed, an interlayer insulating film is formed by a lamination of a nitride film and an oxide film or the like.